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Stock code
688262

Products　|　　Endpoint Security

Product Overview
Functional Characteristics
Typical Application
Technical Support

Security Chip-CCM4202S

CCM4202S is designed with discrete Cortex-M4 and C*Core C0 cores. It is distinguished by low power consumption, high performance, multifunction and high security level. With a security level reaching EAL5+ and Level II of national commercial cypher code standards. it supports Ali ID2 security chip and application specifications. It can be widely used in fingerprint modules, smart door locks, MPOS products, as well as online banking, mobile payment, data security, secure communication, copyright control, and smart grids. The chip’s typical operating frequency is 120MHz.

Block diagram of CCM4202S

Package Type

Pin	Package type and pin assignment(mm)
Pin	QFN32(440.75)	QFN88(10100.75)	BGA121(881.07)
SPI	2	3	3
I2C	1	3	3
SSI	0	1	2
SCI	1	3	3
ISO7816	2	1	2
USB	1(USB1.1)	1(USB1.1)	1(USB_OTG2.0)
ADC	0	3	3
DAC	0	1	1
PWM (Multiplexing)	3	4	4
MCC	0	0	1
TSI (Touchscreen Multiplexing）	8	16	16
EPORT (Multiplexing）	10	40	37
SDIO(Tamper Resistance)	0	1	8
C0 SUB I/O	0	4	8

Functional Characteristics

CPU Features

? 32-bit high-performance Cortex-M4F core
? Operating frequency:120MHz
? Supporting DSP instructions
? Supporting single-precision floating-point unit (FPU)
? Memory protection unit (MPU)
? 16KB Cache
? External bus supports 8bit/16bit/32bit access
? Supporting hardware-secure access control for peripheral components
? Nested Vectored Interrupt Controller (NVIC): low-latency, low-jitter interrupt response
? Low power consumption with high performance
On-Chip Memory Resources

? 224K bytes of SRAM + 32K bytes of TCM SRAM
? 24K bytes of ROM
? 24K bytes of ROM
Internal Modules

? DMA/EDMA
? Timers(2*PIT32bit)
? Watchdog(WDT)
? Time Counter (TC)
? Real-Time Clock (RTC)
? Nested Vectored Interrupt Controller (NVIC)
Security Features

● Asymmetric algorithms

- 1024bit RSA

- 2048bit RSA

- 256bit SM2 prime field

● Symmetric algorithms

- DES/3DES supports ECB/CBC mode

- AES supports ECB/CBC/CTR mode

- SM4 supports ECB/CBC mode

● Hashing algorithms

- SM3

- SHA-0/ SHA-1/ SHA-224/ SHA-256/ SHA-384/ SHA-512
Security Features-CRC

● CRC
- Supporting CRC32/ CRC16/ CRC8
- Supporting DMAC operation
Security Features-Memory protection mechanism

● Memory protection mechanism
- Application-oriented memory partitioning with hardware support for secure isolation
- Scrambling bus
● True random number generator, compliant with FIPS 140-2 standards and national commercial cryptography standards
Security Features-Safety detection and protection unit

? Voltage detection unit
? Light detection unit
? Power supply burr detection unit
? Metal shielding protection
? Temperature detection unit
? Frequency detection unit
? Clock and reset pulse filtering
? Optimizing wire routing for security
Security Features-PCI certification satisfaction

? Supporting 128 Byte NVSRAM
? Supporting 4 pairs of open cover detection signals, configured with dynamic/static detection mode
? Supporting voltage detection
? Supporting temperature detection
? Supporting self-destruct and clear NVSRAM
Other Features

? Each product has a unique serial number
? Main power input voltage: 1.62V~5.5V, PCI domain input voltage: 1.9V~3.63V
? Built-in LDO power output
? Typical power consumption: 120uA/MHz
? Static power consumption: 0.3uA
? Supporting internal power-on reset and external reset
CPU Characteristics

? 32-bit RISC core CS0 with highly optimized 3-stage pipeline
? Operating frequency: 8MHz
? Supporting byte, half-word, and word memory access
? Supporting interrupt nesting
? Fully static design to reduce power consumption
On-chip Storage Resources

? 4K bytes of SRAM
Internal Modules

? Watchdog timer (WDT)
? Time counter (TC)
Other Features

? Independent input voltage: 1.62V~5.5V
? Typical power consumption: 50uA/MHz
? Static power consumption:0.3uA5
Product Qualification

? Level II of security chip for commercial crypto product certification
? EAL5+ of China Cybersecurity Review Technology and Certification Center
? Terminal Chip Security Assessment (compliant with PCI 6.0)